Channel equalization in data receivers

ABSTRACT

Channel equalization in a  1000 BASE-T receiver is performed by a fixed mode analog filter  2  suitable for the longest possible cable length, by a FFE ( 3 ), and by a digital filter  4.  The digital filter ( 4 ) has two sets of taps. One set is optimal for shorter cable lengths and so cancels adaptation for long cable lengths and assists operation of the analog filter. A decision block ( 5 ) selects an appropriate set of taps.

INTRODUCTION

[0001] 1. Field of the Invention

[0002] The invention relates to data receivers such as those for1000BASE-T (“Gigabit”) communication.

[0003] 2. Prior Art Discussion

[0004] Such communication involves compensation for various sources oferror. For example, the response of the cable introduces timedispersion, resulting in intersymbol interference (ISI).

[0005] The primary existing approaches to equalizing the 1000BASE-Tchannel are as follows.

[0006] 1. Analog adaptive equalization. Typically analog equalizersconsist of the sum of a weighted version of the input signal. In thecase of Ethernet (100BASE-T or 1000BASE-T), the fixed filter is designedto equalize the target cable length (say 100 meters). By choosingappropriate weights cable lengths from 0 meters to the target cablelength can be approximately equalized. However such a filter is verycomplex and a large silicon area and power consumption are required. 2.Digital adaptive equalization. Equalization is achieved by means of afeed-forward equalizer (FFE) which consists of a finite impulse response(FIR) filter, whose input is the signal at the output of thecommunication channel (the cable plus other analog and digitalcomponents in the signal path). The FFE coefficients are adapted so thatthe convolution of the impulse response of the channel with the impulseresponse of the FFE approximates a target response. This target responsemay either be fixed or it may be adaptively constructed by means of adecision feedback equalizer (DFE). The DFE is an adaptive filter whoseinput consists of the decisions at the output of a decision device(slicer) and whose output is subtracted from the FFE output before goingto the slicer. The least mean squares (LMS) algorithm is usually used toadapt the coefficients of the equalizer. This algorithm aims to minimisethe mean square error at the slicer. This error will primarily consistof uncanceled ISI and residual additive noise. Such an arrangement isdescribed in European Patent Application EP0467412 (Fujitsu Limited).However, in certain communication systems the decision device (slicer)produces erroneous decisions with too high a probability. This isparticularly the case for Gigabit ethernet communication systems becauseof the positioning of the DFE before a convolutional decoder.

[0007] The main problems with analog equalizers are:

[0008] Its performance assumes a highly simplified channel model, forinstance effects like structural return loss (SRL) are not considered.These effects cannot be cancelled by the analog equalizers.

[0009] Its adaptation algorithm does not take additive noise intoconsideration, therefore it cannot make the right trade-off betweencancelling ISI and attenuating additive noise.

[0010] Some adaptation algorithms have difficulties handling gain oroffset errors.

[0011] The FIR digital equalizer has difficulty handling the cable's lowfrequency effects. These effects tend to last for a long time and aredifficult to cancel by a filter with finite impulse response ofreasonable length. The number of coefficients of the equalizer wouldhave to significantly grow if these effects were to be cancelled with anFIR filter.

[0012] It is proposed in Samulei et al (IEEE Journal on selected Areasin Communications, volume 9, no. 6 August 1991 pages 839-847) and thedocument referenced therein Chen, W. Y. (Proc. 1990 IEEE Int. Symp.Circ. Syst, May 1990 pages 1947-1950), to use an infinite impulseresponse (IIR) filter in conjunction with an FIR filter to reduce thecomplexity of the FIR filter. The IIR filter is adapted to the cablecharacteristics using an LMS- type algorithm. This approach appears torequire considerable area and power in ASIC implementations.

[0013] Also, it is more difficult to meet the performance requirementsat longer cable lengths, however the system bit error rate (BER) needsto be met at all cable lengths.

[0014] The invention is thus directed towards providing for improvedcompensation to address these problems.

SUMMARY OF THE INVENTION

[0015] According to the invention there is provided an equalizationsystem for a data receiver, the system comprising a digital equalizer,characterized in that,

[0016] the digital filter comprises a plurality of fixed sets of taps;

[0017] each said set of taps is suitable for different cablecharacteristics; and

[0018] the equalizer further comprises a decision device comprisingmeans for selecting an optimum set of taps.

[0019] In one embodiment the sets of taps are in an infinite impulseresponse (IIR) structure.

[0020] In one embodiment a set of taps is optimal for shorter cablelengths.

[0021] In another embodiment the system further comprises an analogfilter and said set of taps comprises means for cancelling adaptation ofthe analog filter.

[0022] In a further embodiment a set of taps is optimal for longer cablelengths and comprises means for matching lower frequencies.

[0023] In one embodiment the system further comprises a feed forwardequalizer between the analog filter and the digital filter.

[0024] In one embodiment the decision device comprises means forselecting a set of taps by comparing performance of the system with eachof the sets of taps individually selected.

[0025] In a further embodiment the decision device comprises means forselecting a set of taps at every start-up.

[0026] In one embodiment the decision device comprises a measurementcircuit for measuring the power of the noise output associated with aset of taps.

[0027] In one embodiment the measurement circuit comprises a squarer andan accumulator.

DETAILED DESCRIPTION OF THE INVENTION

[0028] The invention will be more clearly understood from the followingdescription of some embodiments thereof, given by way of example onlywith reference to the accompanying drawings in which:Brief

DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 is a block diagram illustrating equalizer components of theinvention; and

[0030]FIG. 2 is a plot of channel performance.

DESCRIPTION OF THE EMBODIMENTS

[0031] Referring to FIG. 1, equalization components 1 of a 1000BASE-Treceiver comprise an analog filter 2, a feed forward equalizer 3, and adigital filter 4. The output of the digital filter is fed to a decisionblock 5.

[0032] In more detail, the analog filter 2 is not adaptive. It has afixed mode, suitable for much of the adaptation required for the longestpermissible cable length. However, it is ineffective for short lengths.The FFE 3 is conventional.

[0033] The digital filter 4 has two sets of taps in a simple IIRstructure. One set is optimal for shorter cable lengths as it cancelsthe adaptation of the analog filter and also caters for noise arisingfrom SRL and additive noise. The second set is optimal for long cablelengths, and so it assists operation of the analog filter 2. An aspectof the second set of taps is that it matches lower frequencies,something not done effectively by the analog filter 1 or the FFE 3.

[0034] The decision block 5 selects the set of taps appropriate for anyparticular channel. It does this by, at start-up, comparing theperformance of the system with the filter 4 in both settings andselecting the set giving the best signal to noise ratio. A slicer andmeasurement circuitry within the block 5 perform the measurements andcomparisons.

[0035] The measurement circuitry comprises a squarer and an accumulatorfor subtracting the symbols from the combined incoming symbols andnoise.

[0036] In a first setting of the digital filter 4 the block 5 uses thedigital filter output and its own internal squarer and accumulator tomeasure the power of the noise at the digital filter output. After anappropriate time this power is stored and this measurement is repeatedfor the other set of taps. The set of taps providing the lower noisevalue is selected.

[0037] Referring to FIG. 2, it can be seen that the performance improvesfor lengths greater than 50 m where the fixed filter is applied.

[0038] The invention is not limited to the embodiments described but maybe varied in construction and detail.

1. An equalization system for a data receiver, the system comprising adigital equalizer, characterized in that, the digital filter comprises aplurality of fixed sets of taps; each said set of taps is suitable fordifferent cable characteristics; and the equalizer further comprises adecision device comprising means for selecting an optimum set of taps.2. An equalization system for a data receiver as claimed in claim 1,wherein the sets of taps are in an infinite impulse response (IIR)structure.
 3. An equalization system for a data receiver as claimed inclaim 2, wherein a set of taps is optimal for shorter cable lengths. 4.An equalization system for a data receiver as claimed in claim 3,wherein the system further comprises an analog filter and said set oftaps comprises means for cancelling adaptation of the analog filter. 5.An equalization system for a data receiver as claimed in claim 2,wherein a set of taps is optimal for longer cable lengths and comprisesmeans for matching lower frequencies.
 6. An equalization system for adata receiver as claimed in claim 4, wherein the system furthercomprises a feed forward equalizer between the analog filter and thedigital filter.
 7. An equalization system for a data receiver as claimedin claim 1, wherein the decision device comprises means for selecting aset of taps by comparing performance of the system with each of the setsof taps individually selected.
 8. An equalization system for a datareceiver as claimed in claim 7, wherein the decision device comprisesmeans for selecting a set of taps at every start-up.
 9. An equalizationsystem for a data receiver as claimed in claim 7, wherein the decisiondevice comprises a measurement circuit for measuring the power of thenoise output associated with a set of taps.
 10. An equalization systemfor a data receiver as claimed in claim 9, wherein the measurementcircuit comprises a squarer and an accumulator.
 11. A data receivercomprising an equalization system as claimed in claim 1.